Overview
The SHA-384 and SHA-512 Secure Hashing Algorithms were developed by the National Institute
of Standards and Technology (NIST), and are described in FIPS PUB 180-2. They are very similar
64-bit algorithms which may be used to generate either a unique 384-bit or 512-bit "digest"
from an arbitrary length input message, where the digest is a compressed but irreversible
representation of the original message which may be used to determine whether the
message has been altered in transit.
The SHA-384 and SHA-512 algorithms were originally designed to provide matched authentication
for encryption based on AES using the 192-bit and 256-bit keysizes respectively. They are
intended for use in applications such as Digital Signature generation and verification,
and wherever data integrity checking and origin authentication are requirements.
In particular SHA-384 has been specified as a component of the Suite B set of
cryptographic algorithms specified by the US National Security Agency.
Helion SHA-384/512 Solutions
Helion have a number of solutions which implement the SHA-384 and SHA-512 algorithms;
we consider the "Fast" versions here, which are aimed at applications requiring
data throughputs up to the 1 - 2Gbps range.
These powerful building blocks have been designed to offer stand-alone hardware
acceleration of the arithmetically intensive hashing function. Where previously
this function might have been handled in software, modern wire-speeds are exceeding
these capabilities and hardware assistance is becoming a very attractive alternative.
These cores fill this requirement with a well proven, easy to use and efficient solution.
Helion's Fast SHA-384/512 cores aim to offer this functionality at high data rates
whilst occupying only a moderate logic area. They can process both plain hashing,
and keyed HMAC (with optional HMAC wrapper), and can optionally support state
unload and reload part way through a message which may be useful when dealing with
fragmented data.
These high performance cores are available in versions for use in ASIC,
Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results. For more detailed information on these cores,
please download the appropriate datasheet below.
Measured Performance
| TARGET |
MAX THROUGHPUT |
AREA |
ASIC
(0.18um CMOS) |
>TBA Gbps |
<TBA gates |
Altera FPGA
(Cyclone 3 -6) |
>1260 Mbps |
3458 LEs
8 M9K RAMs |
Altera FPGA
(Stratix 2 -3) |
>1745 Mbps |
2153 ALUTs
8 M4K RAMs |
Altera FPGA
(Stratix 3 -2) |
>2295 Mbps |
2071 ALUTs
8 M9K RAMs |
Xilinx FPGA
(Spartan 3E -5) |
>1060 Mbps |
1504 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 4 -11) |
>1660 Mbps |
1487 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 5 -3) |
>2345 Mbps |
606 slices
0 BlockRAMs |
Datasheets
Click here for the SHA-384/512 Altera FPGA core data sheet (PDF format)
Click here for the SHA-384/512 Xilinx FPGA core data sheet (PDF format)
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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