Overview
The SHA-256 Secure Hashing Algorithm was developed by the National Institute
of Standards and Technology (NIST), and is described in FIPS PUB 180-2. It is a
32-bit algorithm which may be used to generate a unique 256-bit "digest"
from an arbitrary length input message, where the digest is a compressed but irreversible
representation of the original message which may be used to determine whether the
message has been altered in transit.
The SHA-256 algorithm was originally designed to provide matched authentication for
encryption based on AES using the 128-bit keysize. It is intended for use in
applications such as Digital Signature generation and verification, and wherever
data integrity checking and origin authentication are requirements. In particular
SHA-256 has been specified as a component of the Suite B set of cryptographic
algorithms specified by the US National Security Agency.
Helion SHA-256 Solutions
Helion have a number of solutions which implement the SHA-256 algorithm;
we consider the "Fast" version here, which is aimed at applications requiring
data throughputs up to the 1 to 2Gbps range.
These powerful building blocks have been designed to offer stand-alone hardware
acceleration of the arithmetically intensive hashing function. Where previously
this function might have been handled in software, modern wire-speeds are exceeding
these capabilities and hardware assistance is becoming a very attractive alternative.
These cores fill this requirement with a well proven, easy to use and efficient solution.
Helion's Fast SHA-256 cores aim to offer this functionality at high data rates
whilst occupying only a moderate logic area. They can process both plain hashing,
and keyed HMAC (with optional HMAC wrapper), and can optionally support state
unload and reload part way through a message which may be useful when dealing with
fragmented data.
These high performance cores are available in versions for use in ASIC,
Actel, Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results. For more detailed information on these cores,
please download the appropriate datasheet below.
Measured Performance
| TARGET |
MAX THROUGHPUT |
AREA |
ASIC
(0.18um CMOS) |
>1.96 Gbps |
<26k gates |
Actel FPGA
(AX -2) |
>698 Mbps |
3135 cells
4 RAMs |
Altera FPGA
(Cyclone 3 -6) |
>768 Mbps |
1815 LEs
4 M9K RAMs |
Altera FPGA
(Stratix 2 -3) |
>1380 Mbps |
1105 ALUTs
4 M4K RAMs |
Altera FPGA
(Stratix 3 -2) |
>1860 Mbps |
1149 ALUTs
4 M9K RAMs |
Xilinx FPGA
(Spartan 3E -5) |
>810 Mbps |
761 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 4 -11) |
>1250 Mbps |
758 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 5 -3) |
>1720 Mbps |
325 slices
0 BlockRAMs |
Datasheets
Click here for the SHA-256 ASIC core data sheet (PDF format)
Click here for the SHA-256 Actel FPGA core data sheet (PDF format)
Click here for the SHA-256 Altera FPGA core data sheet (PDF format)
Click here for the SHA-256 Xilinx FPGA core data sheet (PDF format)
Other SHA-256 Solutions
For applications where fast SHA-1 is a requirement alongside SHA-256, Helion offer dual-mode
cores for both ASIC and supported FPGA technologies.
Please see our Multi-mode hash cores page for full details.
The core described here is aimed at high data rates, but if your requirement is for
lower data rates, you may wish to look at our Compact Hash core, which offers true multi-mode
and HMAC support in a very small footprint in certain FPGA targets. This core is described
in more detail on our Multi-mode hash cores page.
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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