Overview
The SHA-1 Secure Hashing Algorithm was developed by the National Institute of
Standards and Technology (NIST) in 1995 and is described in NIST FIPS PUB 180-2.
It is a 32-bit algorithm which may be used to generate a unique 160-bit "digest"
from an arbitrary length input message. This digest is effectively a compressed
but irreversible representation of the entire input message, and can be used to
determine whether the message has been tampered with in transit. When used as
the basis for an HMAC, it can be keyed to provide additional security, where
it is usually used to provide authentication of data in such applications as
IPsec.
Helion SHA-1 Solutions
Helion have available a number of solutions which implement the SHA-1 algorithm;
we consider the "Fast" version here, which is aimed at applications requiring
data throughputs up to the 1 - 2Gbps range.
These powerful building blocks have been designed to offer stand-alone hardware
acceleration of the arithmetically intensive hashing function. Where previously
this function might have been handled in software, modern wire-speeds are exceeding
these capabilities, and hardware assistance is becoming a very attractive alternative.
These cores fill this requirement with a well proven, easy to use and efficient solution.
Helion's Fast SHA-1 cores aim to offer this functionality at high data rates
whilst occupying only a moderate logic area. They can process both plain hashing,
and keyed HMAC (with optional HMAC wrapper), and can also optionally support state
unload and reload part way through a message, which may be useful when dealing with
fragmented data.
These high performance cores are available in versions for use in ASIC,
Actel, Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results. For more detailed information on these cores,
please download the appropriate datasheet below.
Measured Performance
| TARGET |
MAX THROUGHPUT |
AREA |
ASIC
(0.18um CMOS) |
>1.8 Gbps |
<23k gates |
Actel FPGA
(AX -2) |
>860 Mbps |
1971 cells
4 RAMs |
Altera FPGA
(Cyclone 3 -6) |
>1060 Mbps |
1323 LEs
3 M9K RAMs |
Altera FPGA
(Stratix 2 -3) |
>1540 Mbps |
766 ALUTs
3 M4K RAMs |
Altera FPGA
(Stratix 3 -2) |
>1860 Mbps |
781 ALUTs
3 M9K RAMs |
Xilinx FPGA
(Spartan 3E -5) |
>770 Mbps |
464 slices
0 BlockRAMs |
Xilinx FPGA
(Virtex 4 -11) |
>1240 Mbps |
462 slices
0 BlockRAMs |
Xilinx FPGA
(Virtex 5 -3) |
>1960 Mbps |
209 slices
0 BlockRAMs |
Datasheets
Click here for the ASIC core data sheet (PDF format)
Click here for the Actel FPGA core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)
Other SHA-1 solutions
For applications where fast MD5 or SHA-256 are a requirement alongside SHA-1, Helion offer
dual-mode cores for both ASIC and supported FPGA technologies.
Please see our Multi-mode hash cores page for full details.
The core described here is aimed at high data rates, but if your requirement is for
lower data rates, you may wish to look at our Compact Hash core, which offers true multi-mode
and HMAC support in a very small footprint in certain FPGA targets. This core is described
in more detail on our Multi-mode hash cores page.
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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