Overview
The MD5 message digest algorithm was developed by Ron Rivest for RSA Security,
Inc in 1991 and is described in RFC 1321. It is a 32-bit algorithm which may be
used to generate a unique 128-bit "digest" from an arbitrary length input message.
This digest is effectively a compressed but irreversible representation of the
entire input message, and can be used to determine whether the message has been
tampered with in transit. When used as the basis for an HMAC, it can be keyed
to provide additional security, where it is usually used to provide authentication
of data in such applications as IPsec.
Helion MD5 Solutions
Helion have available a number of solutions which implement the MD5 algorithm;
we consider the "Fast" version here, which is aimed at applications requiring
data throughputs up to the 1 - 2Gbps range.
These powerful building blocks have been designed to offer stand-alone hardware
acceleration of the arithmetically intensive hashing function. Where previously
this function might have been handled in software, modern wire-speeds are exceeding
these capabilities, and hardware assistance is becoming a very attractive alternative.
These cores fill this requirement with a well proven, easy to use and efficient solution.
Helion's Fast MD5 cores aim to offer this functionality at high data rates
whilst occupying only a moderate logic area. They can process both plain hashing,
and keyed HMAC (with optional HMAC wrapper), and can also optionally support state
unload and reload part way through a message, which may be useful when dealing with
fragmented data.
These high performance cores are available in versions for use in ASIC,
Actel, Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results. For more detailed information on these cores,
please download the appropriate datasheet below.
Measured Performance
| TARGET |
MAX THROUGHPUT |
AREA |
ASIC
(0.18um CMOS) |
>1140 Mbps |
<16k gates |
Altera FPGA
(Cyclone 3 -6) |
>770 Mbps |
1423 LEs
4 M9K RAMs |
Altera FPGA
(Stratix 2 -3) |
>1170 Mbps |
1018 ALUTs
4 M4K RAMs |
Altera FPGA
(Stratix 3 -2) |
>1550 Mbps |
958 ALUTs
4 M9K RAMs |
Xilinx FPGA
(Spartan 3E -5) |
>600 Mbps |
697 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 4 -11) |
>945 Mbps |
641 slices
1 BlockRAM |
Xilinx FPGA
(Virtex 5 -3) |
>1345 Mbps |
279 slices
0 BlockRAMs |
Datasheets
Click here for the ASIC core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)
Other MD5 solutions
For applications where fast SHA-1 is a requirement alongside MD5, Helion offer dual-mode
cores for both ASIC and supported FPGA technologies.
Please see our Multi-mode hash cores page for full details.
The core described here is aimed at high data rates, but if your requirement is for
lower data rates, you may wish to look at our Compact Hash core, which offers true multi-mode
and HMAC support in a very small footprint in certain FPGA targets. This core is described
in more detail on our Multi-mode hash cores page.
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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