Overview
The Data Encryption Standard (DES) is a block cipher which was selected as
an official US Federal Information Processing Standard (FIPS) in 1976, and
which has since enjoyed widespread use internationally in many commercial
and government applications.
DES is a 64-bit block cipher, which uses a 56-bit key to encrypt or decrypt
each block of data. In recent years, ordinary single DES has been considered
to be too insecure for many applications, and so is rarely used today; this is
primarily due to its 56-bit key size being too small, such that DES keys can
be broken by brute force within reasonably short time periods.
The DES algorithm is however believed to be practically secure in the form of
Triple DES (3DES), where single DES is essentially used three times over,
and sometimes referred to as "EDE" - an encrypt, followed by a decrypt, followed by
another encrypt, each with different 56-bit keys. This increases the effective
key length, thereby improving security.
In recent years 3DES has been largely superseded by the
Advanced Encryption Standard (AES), however it is still used in such
protocols as IPsec, where it is a baseline requirement for full compliance
to the standard.
Helion DES & 3DES Solutions
Helion offer a range of high performance DES and 3DES cores in versions for
use in ASIC, Actel, Altera, Lattice and Xilinx FPGA, which implement the DES
and 3DES algorithms as described in FIPS publication 46-3. They are available
in three versions; STANDARD, FAST and V FAST, each offering a different speed/area
balance, with the fastest solution capable of supporting Gigabit 3DES throughputs
in ASIC.
Having the choice of three versions gives you the benefit of being able to
use a very closely matched solution to your needs, meaning less area and power
for a given application.
The Helion DES cores have been designed to be extremely easy to integrate
into any target system, whatever the specific requirements. They support
both encryption and decryption, and in 3DES mode the core can optionally
implement two or three key 3DES. They also offer full support for any of
the block cipher modes (eg. CBC, CFB, OFB, Counter) with the addition of
simple mode wrapper logic; reference designs for these can be supplied with
the core on request.
Moreover, the Helion DES cores have been designed to be especially fast
and space efficient, without having to resort to extensive pipelining.
This means that even the fastest Gigabit solutions can support feedback
modes such as CBC, and offer low latency operation within your system.
Typical Performance
Example throughput figures for Triple DES ECB Encryption/Decryption
| |
STANDARD |
FAST |
V FAST |
ASIC
(0.13um CMOS) |
>320 Mbps |
>500 Mbps |
>1 Gbps |
Actel FPGA
(ProASIC3 -2) |
>115 Mbps |
>150 Mbps |
N/A |
Altera FPGA
(Cyclone 2 -6) |
>270 Mbps |
>355 Mbps |
N/A |
Altera FPGA
(Stratix 2 -3) |
>410 Mbps |
>535 Mbps |
N/A |
Xilinx FPGA
(Spartan 3 -5) |
>195 Mbps |
>265 Mbps |
N/A |
Xilinx FPGA
(Virtex 4 -11) |
>350 Mbps |
>500 Mbps |
N/A |
Xilinx FPGA
(Virtex 5 -3) |
>525 Mbps |
>770 Mbps |
N/A |
Datasheets
Click here for the ASIC core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)
Click here for the Actel FPGA core data sheet (PDF format)
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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