Overview
The AES-XTS algorithm is in a class known as "Tweakable" block ciphers,
more specifically an application specific version of a mode called AES-XEX,
specified by the IEEE 1619 working group in their standard for disk encryption,
taking over from the previously specified LRW-AES algorithm.
In this application, AES-XTS is used to encrypt data at the disk sector level,
where it addresses threats such as copy-and-paste attacks and dictionary attacks,
while allowing the option of parallel processing for enhanced performance.
When used for disk encryption, AES-XTS encrypts and decrypts blocks of 16-bytes
at a time under the control of a secret AES key, and a "tweak" value derived
from the logical position of the block on the disk. This algorithm fulfils
the fundamental requirements for disk encryption, in that the data can be independently
encrypted and decrypted at the sector level as it arrives in arbitrary order, and that
the encryption process does not change the data size. In addition, the location of the
data on the disk will vary the encrypted result, so that identical plaintext sectors
stored at different places on the disk will be different after encryption.
Helion AES-XTS Solutions
Helion offer a suite of AES-XTS solutions which allow the user to choose a level of
hardware acceleration which closely fits the requirements, therefore minimising the
amount of logic resources required. Solutions are available covering all throughput
requirements from less than 1Gbps right up to in excess of 30Gbps in any of the
target technologies we support. Also available are combined solutions which implement
AES-XTS together with other modes of AES such as AES-GCM or
AES-CBC, where multi protocol support is desired.
These high performance cores are available in versions for use in ASIC,
Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results.
To find out how these AES-XTS solutions can be used in your particular application,
please check out the datasheets below, or contact Helion so that we can discuss
the options in more detail.
Datasheets
For full details of the Helion AES-XTS cores, please download the datasheet appropriate
to your target technology.
Click here for the Xilinx FPGA core data sheet (PDF format)
ASIC & Altera FPGA datasheets are available on request.
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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