Overview
The Helion AES Key Wrap Cores implement the AES Key Wrap and Unwrap algorithms
as described in the NIST AES Key Wrap Specification (November 2001). They also fully support
the AESKW algorithm proposed in the draft key wrap standard, ANS X9.102. They are
ideally suited for protecting cryptographic keys within applications where the
key material must either be transmitted over insecure communication channels,
or stored within untrusted environments where required by the Key Management scheme.
In November 2004, the American Standards Committee X9 requested the review of four different
key wrap algorithms which are described in the draft key wrap standard, ANS X9.102. One of the
proposed algorithms, AESKW, is a variant of the original NIST AES Key Wrap Specification which
is fully supported by the Helion AES Key Wrap cores. Currently the draft key wrap standard has
yet to be ratified and issued as a full standard.
Helion AES Key Wrap Solutions
The Helion AES Key Wrap solutions are compliant with the AESKW algorithm proposed in ANS X9.102 and
are available as separate Key Wrap and Key Unwrap cores to provide maximum flexibility and
optimal resource usage. Both cores can support all three AES key sizes (128, 192 and 256 bits),
and are available in two performance variants ("Tiny" and "Standard") which can be chosen according to
what wrap or unwrap latency your application requires.
The maximum key data length supported is technology specific, and is indicated in the datasheets below.
Since the maximum key data size will vary for each user application, Helion can easily provide a
customised solution based on its Key Wrap cores if the standard supported length is insufficient.
Measured Area
The figures below show the typical resource requirements for the Tiny version of the Key Wrap and
Unwrap cores with support for all AES key sizes (128, 192, and 256-bit) in different target technologies:
| TARGET |
KEY WRAP CORE |
KEY UNWRAP CORE |
Actel FPGA
(ProASIC3) |
1288 tiles
3 RAMs |
1507 tiles
3 RAMs |
Xilinx FPGA
(Spartan 3) |
260 slices
2 BlockRAMs |
302 slices
2 BlockRAMs |
Xilinx FPGA
(Virtex 4) |
262 slices
2 BlockRAMs |
302 slices
2 BlockRAMs |
Xilinx FPGA
(Virtex 5) |
119 slices
1 BlockRAM |
135 slices
1 BlockRAM |
Altera FPGA
(Cyclone II) |
675 LEs
3 M4Ks |
786 LEs
3 M4Ks |
Altera FPGA
(Cyclone III) |
693 LEs
3 M9Ks |
788 LEs
3 M9Ks |
Altera FPGA
(Stratix II) |
383 ALMs
3 M4Ks |
411 ALMs
3 M4Ks |
Datasheets
For full details of the Helion AES Key Wrap core family, please download the datasheet appropriate to your target technology.
Please note that for Xilinx only there are separate datasheets for the Key Wrap and Key Unwrap cores, which are both
available in either Tiny or Standard versions. Other technologies currently only come in the Tiny variant.
Click here for the Actel FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA Key Wrap core data sheet (PDF format)
Click here for the Xilinx FPGA Key Unwrap core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)
Contact
For more detailed information on this or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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