Overview
The Helion AES Key Wrap Cores implement the AES Key Wrap and Unwrap algorithms
as described in the NIST AES Key Wrap Specification (November 2001). They also fully support
the AESKW algorithm proposed in the draft key wrap standard, ANS X9.102. They are
ideally suited for protecting cryptographic keys within applications where the
key material must either be transmitted over insecure communication channels,
or stored within untrusted environments where required by the Key Management scheme.
In November 2004, the American Standards Committee X9 requested the review of four different
key wrap algorithms which are described in the draft key wrap standard, ANS X9.102. One of the
proposed algorithms, AESKW, is a variant of the original NIST AES Key Wrap Specification which
is fully supported by the Helion AES Key Wrap cores. Currently the draft key wrap standard has
yet to be ratified and issued as a full standard.
Helion AES Key Wrap Solutions
The Helion AES Key Wrap solution is compliant with the AESKW algorithm proposed in ANS X9.102 and
is available as separate Key Wrap and Key Unwrap cores to provide maximum flexibility and
optimal resource usage. Both cores support all three AES key sizes (128, 192 and 256 bits), and key
data lengths of up to 16,064 bits in Xilinx FPGA technology.
Since the maximum key data size will vary depending on the application, Helion can easily provide
a customised solution based on its Key Wrap cores. Please contact us for further details should
our standard solutions not match your system requirements.
Measured Area
The figures below show the resource usage for the Key Wrap and Unwrap cores with support
for all AES key sizes (128, 192, and 256-bit) in different target technologies:
| TARGET |
KEY WRAP CORE |
KEY UNWRAP CORE |
Actel FPGA
(ProASIC3 -2) |
1288 tiles
3 RAMs |
1507 tiles
3 RAMs |
Xilinx FPGA
(Spartan 3 -5) |
249 slices
2 BlockRAMs |
290 slices
2 BlockRAMs |
Xilinx FPGA
(Virtex 4 -11) |
248 slices
2 BlockRAMs |
289 slices
2 BlockRAMs |
Xilinx FPGA
(Virtex 5 -3) |
116 slices
1 BlockRAM |
133 slices
1 BlockRAM |
Datasheets
For full details of the Helion AES Key Wrap cores, please download the datasheet appropriate to your target technology.
An ASIC version of the cores will be available in Q3 08. Altera FPGA versions are available on request.
Click here for the Actel FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)
Contact
For more detailed information on this or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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