Overview
AES-GCM is an authenticated encryption algorithm designed to provide both authentication
and privacy. Developed by David A McGrew and John Viega, it uses universal hashing over
a binary Galois field to provide authenticated encryption.
GCM was designed originally as a way of supporting very high data rates, since it can take
advantage of pipelining and parallel processing techniques to bypass the normal limits imposed
by feedback MAC algorithms. This allows authenticated encryption at data rates of many tens
of Gbps, permitting high grade encryption and authentication on systems which previously could
not be fully protected. More recently GCM is being specified for use in lower rate applications
due to its ease of use and scalability.
AES-GCM is specified for use in a number of recent standards; for example it is one of
the options specified by the IEEE 1619 group for securing data-at-rest stored on tape media.
In networking, it is the security algorithm specified for use in MACsec (802.1AE),
and in the ANSI Fibre Channel Security Protocols (FC-SP).
Helion AES-GCM Solutions
Helion offer a broad selection of AES-GCM solutions, covering all throughput requirements
from less than 50Mbps right up to in excess of 30Gbps in any of the target technologies
we support. This allows the user to have a very well matched solution, without having to
compromise in terms of area or performance.
| Core type |
Typical Throughput |
Footprint |
| 218-cycle AES-GCM |
0 to 100Mbps |
ultra compact |
| 48-cycle AES-GCM |
0 to 500Mbps |
very compact |
| 19-cycle AES-GCM |
500Mbps to 2Gbps |
compact |
| Giga GCM |
2Gbps to 30Gbps |
scalable |
The table above shows the selection of standard AES-GCM solutions currently available
from Helion. For the mainstream versions, the core name reflects the nominal number of
clock cycles taken to encrypt or decrypt each 16-byte block of information with a
128-bit key; so for example, the 19-cycle core processes each 128-bit AES block in
19 clock cycles, and has a throughput of 6.73Mbps per MHz.
The Giga GCM core is a separate product, optimised for extremely high throughput
operation; please see the special Giga AES webpage
for more details.
Also available are combined solutions which implement AES-GCM together with other
modes of AES such as AES-XTS (previously known as AES-XEX)
or AES-CCM, where multi protocol support is desired.
All these high performance AES-GCM cores are available in versions for use in ASIC,
Actel, Altera and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results.
To find out how these AES-GCM solutions can be used in your particular application,
please contact Helion so that we can discuss the options in more detail.
Measured Area and Performance
48-cycle 128-bit key version - for low/mid rate applications
| TARGET |
TYPICAL THROUGHPUT |
AREA |
ASIC
(0.13um CMOS) |
>800 Mbps |
<TBA gates |
Actel FPGA
(ProASIC3 -2) |
>240 Mbps |
4293 tiles
3 RAMs |
Altera FPGA
(Cyclone 3 -6) |
>430 Mbps |
1925 LEs
3 M9K RAMs |
Altera FPGA
(Stratix 2 -3) |
>640 Mbps |
1136 ALMs
3 M4K RAMs |
Xilinx FPGA
(Spartan 3 -5) |
>440 Mbps |
698 slices
3 BlockRAMs |
Xilinx FPGA
(Virtex 4 -11) |
>690 Mbps |
717 slices
3 BlockRAMs |
Xilinx FPGA
(Virtex 5 -3) |
>800 Mbps |
415 slices
0 BlockRAMs |
19-cycle 128-bit key version - for higher rate applications
| TARGET |
TYPICAL THROUGHPUT |
AREA |
ASIC
(0.13um CMOS) |
>2.5 Gbps |
<TBA gates |
Actel FPGA
(ProASIC3 -2) |
>680 Mbps |
5618 tiles
10 RAMs |
Xilinx FPGA
(Spartan 3 -5) |
>860 Mbps |
1133 slices
9 BlockRAMs |
Xilinx FPGA
(Virtex 4 -11) |
>1.4 Gbps |
1133 slices
9 BlockRAMs |
Xilinx FPGA
(Virtex 5 -3) |
>1.9 Gbps |
670 slices
0 BlockRAMs |
Remember that these are just two examples from a suite of many AES-GCM solutions
we have available, so if you are looking for lower area or higher rate GCM cores,
support for non-listed target technologies or maybe support for the longer keysizes,
please contact Helion for full information.
Datasheets
For full details of the Helion AES-GCM cores, please download the datasheet
appropriate to your target technology. Datasheets for ASIC targets and for
core versions not covered below, please contact Helion.
Click here for the Actel FPGA core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)
Contact
For more detailed information on these or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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